User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 642 of 909 2019 Ambiq Micro, Inc.
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This register holds the compare limits for timer half A.
13.21.2.52CMPRB7 Register
Counter/Timer B7 Compare Registers
OFFSET: 0x000000E8
INSTANCE 0 ADDRESS: 0x400080E8
This register holds the compare limits for timer half B.
13.21.2.53CTRL7 Register
Counter/Timer Control
OFFSET: 0x000000EC
INSTANCE 0 ADDRESS: 0x400080EC
This register holds the control bit fields for both halves of timer 7.
Table 921: CMPRA7 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1A7 CMPR0A7
Table 922: CMPRA7 Register Bits
Bit Name Reset RW Description
31:16 CMPR1A7 0x0 RW
Counter/Timer A7 Compare Register 1.
15:0 CMPR0A7 0x0 RW
Counter/Timer A7 Compare Register 0.
Table 923: CMPRB7 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1B7 CMPR0B7
Table 924: CMPRB7 Register Bits
Bit Name Reset RW Description
31:16 CMPR1B7 0x0 RW
Counter/Timer B3 Compare Register 1.
15:0 CMPR0B7 0x0 RW
Counter/Timer B3 Compare Register 0.