User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 629 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
13.21.2.40CMPRAUXA5 Register
Counter/Timer A5 Compare Registers
OFFSET: 0x000000B4
INSTANCE 0 ADDRESS: 0x400080B4
Enhanced compare limits for timer half A.
13.21.2.41CMPRAUXB5 Register
Counter/Timer B5 Compare Registers
OFFSET: 0x000000B8
INSTANCE 0 ADDRESS: 0x400080B8
Enhanced compare limits for timer half B.
0 TMRA5EN 0x0 RW
Counter/Timer A5 Enable bit.
DIS = 0x0 - Counter/Timer A5 Disable.
EN = 0x1 - Counter/Timer A5 Enable.
Table 899: CMPRAUXA5 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3A5 CMPR2A5
Table 900: CMPRAUXA5 Register Bits
Bit Name Reset RW Description
31:16 CMPR3A5 0x0 RW
Counter/Timer A5 Compare Register 3. Holds the upper limit for timer half
A.
15:0 CMPR2A5 0x0 RW
Counter/Timer A5 Compare Register 2. Holds the lower limit for timer half A.
Table 901: CMPRAUXB5 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3B5 CMPR2B5
Table 898: CTRL5 Register Bits
Bit Name Reset RW Description