User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 625 of 909 2019 Ambiq Micro, Inc.
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13.21.2.39CTRL5 Register
Counter/Timer Control
OFFSET: 0x000000AC
INSTANCE 0 ADDRESS: 0x400080AC
Control bit fields for both halves of timer 0.
Table 896: CMPRB5 Register Bits
Bit Name Reset RW Description
31:16 CMPR1B5 0x0 RW
Counter/Timer B5 Compare Register 1.
15:0 CMPR0B5 0x0 RW
Counter/Timer B5 Compare Register 0.
Table 897: CTRL5 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTLINK5
RSVD
TMRB5POL TMRB5CLR
TMRB5IE1 TMRB5IE0
TMRB5FN
TMRB5CLK
TMRB5EN
RSVD
TMRA5POL TMRA5CLR
TMRA5IE1 TMRA5IE0
TMRA5FN
TMRA5CLK
TMRA5EN
Table 898: CTRL5 Register Bits
Bit Name Reset RW Description
31 CTLINK5 0x0 RW
Counter/Timer A5/B5 Link bit.
TWO_16BIT_TIMERS = 0x0 - Use A5/B5 timers as two independent 16-bit
timers (default).
32BIT_TIMER = 0x1 - Link A5/B5 timers into a single 32-bit timer.
30:29 RSVD 0x0 RO
RESERVED
28 TMRB5POL 0x0 RW
Counter/Timer B5 output polarity.
NORMAL = 0x0 - The polarity of the TMRPINB5 pin is the same as the timer
output.
INVERTED = 0x1 - The polarity of the TMRPINB5 pin is the inverse of the
timer output.
27 TMRB5CLR 0x0 RW
Counter/Timer B5 Clear bit.
RUN = 0x0 - Allow counter/timer B5 to run
CLEAR = 0x1 - Holds counter/timer B5 at 0x0000.