User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 624 of 909 2019 Ambiq Micro, Inc.
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13.21.2.37CMPRA5 Register
Counter/Timer A5 Compare Registers
OFFSET: 0x000000A4
INSTANCE 0 ADDRESS: 0x400080A4
This register holds the compare limits for timer half A.
13.21.2.38CMPRB5 Register
Counter/Timer B5 Compare Registers
OFFSET: 0x000000A8
INSTANCE 0 ADDRESS: 0x400080A8
This register holds the compare limits for timer half B.
Table 892: TMR5 Register Bits
Bit Name Reset RW Description
31:16 CTTMRB5 0x0 RO
Counter/Timer B5.
15:0 CTTMRA5 0x0 RO
Counter/Timer A5.
Table 893: CMPRA5 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1A5 CMPR0A5
Table 894: CMPRA5 Register Bits
Bit Name Reset RW Description
31:16 CMPR1A5 0x0 RW
Counter/Timer A5 Compare Register 1.
15:0 CMPR0A5 0x0 RW
Counter/Timer A5 Compare Register 0.
Table 895: CMPRB5 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1B5 CMPR0B5