User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 623 of 909 2019 Ambiq Micro, Inc.
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13.21.2.36TMR5 Register
Counter/Timer Register
OFFSET: 0x000000A0
INSTANCE 0 ADDRESS: 0x400080A0
This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count
when the pair is linked.
13 TMRA4POL23 0x0 RW
Counter/Timer A4 Upper output polarity
NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA4TINV 0x0 RW
Counter/Timer A4 Invert on trigger.
DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11
TMRA4NO-
SYNC
0x0 RW
Source clock synchronization control.
DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA4TRIG 0x0 RW
Counter/Timer A4 Trigger Select.
DIS = 0x0 - Trigger source is disabled.
STIMER = 0x1 - Trigger source is STimer Interrupt. Only Active When
CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER inter-
rupt
B4OUT = 0x1 - Trigger source is CTIMERB4 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A6OUT = 0x4 - Trigger source is CTIMERA6 OUT.
B6OUT = 0x5 - Trigger source is CTIMERB6 OUT.
A2OUT = 0x6 - Trigger source is CTIMERA2 OUT.
B2OUT = 0x7 - Trigger source is CTIMERB2 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A1OUT2 = 0xA - Trigger source is CTIMERA1 OUT2.
B1OUT2 = 0xB - Trigger source is CTIMERB1 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
6:0 TMRA4LMT 0x0 RW
Counter/Timer A4 Pattern Limit Count.
Table 891: TMR5 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTTMRB5 CTTMRA5
Table 890: AUX4 Register Bits
Bit Name Reset RW Description