User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 620 of 909 2019 Ambiq Micro, Inc.
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13.21.2.33CMPRAUXA4 Register
Counter/Timer A4 Compare Registers
OFFSET: 0x00000094
INSTANCE 0 ADDRESS: 0x40008094
Enhanced compare limits for timer half A.
13.21.2.34CMPRAUXB4 Register
Counter/Timer B4 Compare Registers
OFFSET: 0x00000098
INSTANCE 0 ADDRESS: 0x40008098
Enhanced compare limits for timer half B.
0 TMRA4EN 0x0 RW
Counter/Timer A4 Enable bit.
DIS = 0x0 - Counter/Timer A4 Disable.
EN = 0x1 - Counter/Timer A4 Enable.
Table 885: CMPRAUXA4 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3A4 CMPR2A4
Table 886: CMPRAUXA4 Register Bits
Bit Name Reset RW Description
31:16 CMPR3A4 0x0 RW
Counter/Timer A4 Compare Register 3. Holds the upper limit for timer half
A.
15:0 CMPR2A4 0x0 RW
Counter/Timer A4 Compare Register 2. Holds the lower limit for timer half A.
Table 887: CMPRAUXB4 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3B4 CMPR2B4
Table 884: CTRL4 Register Bits
Bit Name Reset RW Description