User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 616 of 909 2019 Ambiq Micro, Inc.
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13.21.2.32CTRL4 Register
Counter/Timer Control
OFFSET: 0x0000008C
INSTANCE 0 ADDRESS: 0x4000808C
Control bit fields for both halves of timer 4.
Table 881: CMPRB4 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1B4 CMPR0B4
Table 882: CMPRB4 Register Bits
Bit Name Reset RW Description
31:16 CMPR1B4 0x0 RW
Counter/Timer B4 Compare Register 1. Holds the upper limit for timer half
B.
15:0 CMPR0B4 0x0 RW
Counter/Timer B4 Compare Register 0. Holds the lower limit for timer half B.
Table 883: CTRL4 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTLINK4
RSVD
TMRB4POL TMRB4CLR
TMRB4IE1 TMRB4IE0
TMRB4FN
TMRB4CLK
TMRB4EN
RSVD
TMRA4POL TMRA4CLR
TMRA4IE1 TMRA4IE0
TMRA4FN
TMRA4CLK
TMRA4EN
Table 884: CTRL4 Register Bits
Bit Name Reset RW Description
31 CTLINK4 0x0 RW
Counter/Timer A4/B4 Link bit.
TWO_16BIT_TIMERS = 0x0 - Use A4/B4 timers as two independent 16-bit
timers (default).
32BIT_TIMER = 0x1 - Link A4/B4 timers into a single 32-bit timer.
30:29 RSVD 0x0 RO
RESERVED