User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 615 of 909 2019 Ambiq Micro, Inc.
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13.21.2.30CMPRA4 Register
Counter/Timer A4 Compare Registers
OFFSET: 0x00000084
INSTANCE 0 ADDRESS: 0x40008084
Compare limits for timer half A.
13.21.2.31CMPRB4 Register
Counter/Timer B4 Compare Registers
OFFSET: 0x00000088
INSTANCE 0 ADDRESS: 0x40008088
Compare limits for timer half B.
Table 877: TMR4 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTTMRB4 CTTMRA4
Table 878: TMR4 Register Bits
Bit Name Reset RW Description
31:16 CTTMRB4 0x0 RO
Counter/Timer B4.
15:0 CTTMRA4 0x0 RO
Counter/Timer A4.
Table 879: CMPRA4 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1A4 CMPR0A4
Table 880: CMPRA4 Register Bits
Bit Name Reset RW Description
31:16 CMPR1A4 0x0 RW
Counter/Timer A4 Compare Register 1. Holds the upper limit for timer half
A.
15:0 CMPR0A4 0x0 RW
Counter/Timer A4 Compare Register 0. Holds the lower limit for timer half A.