User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 614 of 909 2019 Ambiq Micro, Inc.
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13.21.2.29TMR4 Register
Counter/Timer Register
OFFSET: 0x00000080
INSTANCE 0 ADDRESS: 0x40008080
This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count
when the pair is linked.
21:16 TMRB3LMT 0x0 RW
Counter/Timer B3 Pattern Limit Count.
15 RSVD 0x0 RO
RESERVED
14 TMRA3EN23 0x0 RW
Counter/Timer A3 Upper compare enable.
DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
13 TMRA3POL23 0x0 RW
Counter/Timer A3 Upper output polarity
NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
12 TMRA3TINV 0x0 RW
Counter/Timer A3 Invert on trigger.
DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger
11
TMRA3NO-
SYNC
0x0 RW
Source clock synchronization control.
DIS = 0x0 - Synchronization on source clock
NOSYNC = 0x1 - No synchronization on source clock
10:7 TMRA3TRIG 0x0 RW
Counter/Timer A3 Trigger Select.
DIS = 0x0 - Trigger source is disabled.
B3OUT = 0x1 - Trigger source is CTIMERB3 OUT.
B2OUT = 0x2 - Trigger source is CTIMERB2 OUT.
A2OUT = 0x3 - Trigger source is CTIMERA2 OUT.
A4OUT = 0x4 - Trigger source is CTIMERA4 OUT.
B4OUT = 0x5 - Trigger source is CTIMERB4 OUT.
A7OUT = 0x6 - Trigger source is CTIMERA7 OUT.
B7OUT = 0x7 - Trigger source is CTIMERB7 OUT.
B5OUT2 = 0x8 - Trigger source is CTIMERB5 OUT2.
A5OUT2 = 0x9 - Trigger source is CTIMERA5 OUT2.
A1OUT2 = 0xA - Trigger source is CTIMERA1 OUT2.
B1OUT2 = 0xB - Trigger source is CTIMERB1 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B2OUT2DUAL = 0xE - Trigger source is CTIMERB2 OUT2, dual edge.
A2OUT2DUAL = 0xF - Trigger source is CTIMERA2 OUT2, dual edge.
6:0 TMRA3LMT 0x0 RW
Counter/Timer A3 Pattern Limit Count.
Table 876: AUX3 Register Bits
Bit Name Reset RW Description