User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 607 of 909 2019 Ambiq Micro, Inc.
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13.21.2.25CTRL3 Register
Counter/Timer Control
OFFSET: 0x0000006C
INSTANCE 0 ADDRESS: 0x4000806C
This register holds the control bit fields for both halves of timer 3.
Table 867: CMPRB3 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1B3 CMPR0B3
Table 868: CMPRB3 Register Bits
Bit Name Reset RW Description
31:16 CMPR1B3 0x0 RW
Counter/Timer B3 Compare Register 1.
15:0 CMPR0B3 0x0 RW
Counter/Timer B3 Compare Register 0.
Table 869: CTRL3 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTLINK3
RSVD
TMRB3POL
TMRB3CLR
TMRB3IE1
TMRB3IE0
TMRB3FN
TMRB3CLK
TMRB3EN
ADCEN
RSVD
TMRA3POL
TMRA3CLR
TMRA3IE1
TMRA3IE0
TMRA3FN
TMRA3CLK
TMRA3EN
Table 870: CTRL3 Register Bits
Bit Name Reset RW Description
31 CTLINK3 0x0 RW
Counter/Timer A3/B3 Link bit.
TWO_16BIT_TIMERS = 0x0 - Use A3/B3 timers as two independent 16-bit
timers (default).
32BIT_TIMER = 0x1 - Link A3/B3 timers into a single 32-bit timer.
30:29 RSVD 0x0 RO
RESERVED