User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 599 of 909 2019 Ambiq Micro, Inc.
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13.21.2.18CTRL2 Register
Counter/Timer Control
OFFSET: 0x0000004C
INSTANCE 0 ADDRESS: 0x4000804C
This register holds the control bit fields for both halves of timer 2.
Table 855: CTRL2 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTLINK2
RSVD
TMRB2POL TMRB2CLR
TMRB2IE1 TMRB2IE0
TMRB2FN
TMRB2CLK
TMRB2EN
RSVD
TMRA2POL TMRA2CLR
TMRA2IE1 TMRA2IE0
TMRA2FN
TMRA2CLK
TMRA2EN
Table 856: CTRL2 Register Bits
Bit Name Reset RW Description
31 CTLINK2 0x0 RW
Counter/Timer A2/B2 Link bit.
TWO_16BIT_TIMERS = 0x0 - Use A2/B2 timers as two independent 16-bit
timers (default).
32BIT_TIMER = 0x1 - Link A2/B2 timers into a single 32-bit timer.
30:29 RSVD 0x0 RO
RESERVED
28 TMRB2POL 0x0 RW
Counter/Timer B2 output polarity.
NORMAL = 0x0 - The polarity of the TMRPINB2 pin is the same as the timer
output.
INVERTED = 0x1 - The polarity of the TMRPINB2 pin is the inverse of the
timer output.
27 TMRB2CLR 0x0 RW
Counter/Timer B2 Clear bit.
RUN = 0x0 - Allow counter/timer B2 to run
CLEAR = 0x1 - Holds counter/timer B2 at 0x0000.
26 TMRB2IE1 0x0 RW
Counter/Timer B2 Interrupt Enable bit for COMPR1.
DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on
COMPR1.
EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COM-
PR1.
25 TMRB2IE0 0x0 RW
Counter/Timer B2 Interrupt Enable bit for COMPR0.
DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on
COMPR0.
EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COM-
PR0