User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 597 of 909 2019 Ambiq Micro, Inc.
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13.21.2.15TMR2 Register
Counter/Timer Register
OFFSET: 0x00000040
INSTANCE 0 ADDRESS: 0x40008040
This register holds the running time or event count for ctimer 2. This is either for each 16 bit half or for the
whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks
and are completely independent.
10:7 TMRA1TRIG 0x0 RW
Counter/Timer A1 Trigger Select.
DIS = 0x0 - Trigger source is disabled.
B1OUT = 0x1 - Trigger source is CTIMERB1 OUT.
B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.
A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.
A0OUT = 0x4 - Trigger source is CTIMERA0 OUT.
B0OUT = 0x5 - Trigger source is CTIMERB0 OUT.
A5OUT = 0x6 - Trigger source is CTIMERA5 OUT.
B5OUT = 0x7 - Trigger source is CTIMERB5 OUT.
B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.
A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.
A4OUT2 = 0xA - Trigger source is CTIMERA4 OUT2.
B4OUT2 = 0xB - Trigger source is CTIMERB4 OUT2.
A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.
A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.
B5OUT2DUAL = 0xE - Trigger source is CTIMERB5 OUT2, dual edge.
A5OUT2DUAL = 0xF - Trigger source is CTIMERA5 OUT2, dual edge.
6:0 TMRA1LMT 0x0 RW
Counter/Timer A1 Pattern Limit Count.
Table 849: TMR2 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTTMRB2 CTTMRA2
Table 850: TMR2 Register Bits
Bit Name Reset RW Description
31:16 CTTMRB2 0x0 RO
Counter/Timer B2.
15:0 CTTMRA2 0x0 RO
Counter/Timer A2.
Table 848: AUX1 Register Bits
Bit Name Reset RW Description