User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 595 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
13.21.2.14AUX1 Register
Counter/Timer Auxiliary
OFFSET: 0x0000003C
INSTANCE 0 ADDRESS: 0x4000803C
Control bit fields for both halves of timer 0.
Table 846: CMPRAUXB1 Register Bits
Bit Name Reset RW Description
31:16 CMPR3B1 0x0 RW
Counter/Timer B1 Compare Register 3. Holds the upper limit for timer half
B.
15:0 CMPR2B1 0x0 RW
Counter/Timer B1 Compare Register 2. Holds the lower limit for timer half B.
Table 847: AUX1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
TMRB1EN23
TMRB1POL23
TMRB1TINV
TMRB1NOSYNC
TMRB1TRIG
RSVD
TMRB1LMT
RSVD
TMRA1EN23
TMRA1POL23
TMRA1TINV
TMRA1NOSYNC
TMRA1TRIG
TMRA1LMT
Table 848: AUX1 Register Bits
Bit Name Reset RW Description
31 RSVD 0x0 RO
RESERVED
30 TMRB1EN23 0x0 RW
Counter/Timer B1 Upper compare enable.
DIS = 0x1 - Disable enhanced functions.
EN = 0x0 - Enable enhanced functions.
29 TMRB1POL23 0x0 RW
Upper output polarity
NORM = 0x0 - Upper output normal polarity
INV = 0x1 - Upper output inverted polarity.
28 TMRB1TINV 0x0 RW
Counter/Timer B1 Invert on trigger.
DIS = 0x0 - Disable invert on trigger
EN = 0x1 - Enable invert on trigger