User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 594 of 909 2019 Ambiq Micro, Inc.
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13.21.2.12CMPRAUXA1 Register
Counter/Timer A1 Compare Registers
OFFSET: 0x00000034
INSTANCE 0 ADDRESS: 0x40008034
Enhanced compare limits for timer half A. This is valid if timer 1 is set to function 4 and function 5.
13.21.2.13CMPRAUXB1 Register
Counter/Timer B1 Compare Registers
OFFSET: 0x00000038
INSTANCE 0 ADDRESS: 0x40008038
Enhanced compare limits for timer half B. This is valid if timer 1 is set to function 4 and function 5.
0 TMRA1EN 0x0 RW
Counter/Timer A1 Enable bit.
DIS = 0x0 - Counter/Timer A1 Disable.
EN = 0x1 - Counter/Timer A1 Enable.
Table 843: CMPRAUXA1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3A1 CMPR2A1
Table 844: CMPRAUXA1 Register Bits
Bit Name Reset RW Description
31:16 CMPR3A1 0x0 RW
Counter/Timer A1 Compare Register 3. Holds the upper limit for timer half
A.
15:0 CMPR2A1 0x0 RW
Counter/Timer A1 Compare Register 2. Holds the lower limit for timer half A.
Table 845: CMPRAUXB1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3B1 CMPR2B1
Table 842: CTRL1 Register Bits
Bit Name Reset RW Description