User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 590 of 909 2019 Ambiq Micro, Inc.
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13.21.2.11CTRL1 Register
Counter/Timer Control
OFFSET: 0x0000002C
INSTANCE 0 ADDRESS: 0x4000802C
This includes the Control bit fields for both halves of timer 1.
Table 839: CMPRB1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1B1 CMPR0B1
Table 840: CMPRB1 Register Bits
Bit Name Reset RW Description
31:16 CMPR1B1 0x0 RW
Counter/Timer B1 Compare Register 1.
15:0 CMPR0B1 0x0 RW
Counter/Timer B1 Compare Register 0.
Table 841: CTRL1 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTLINK1
RSVD
TMRB1POL
TMRB1CLR
TMRB1IE1 TMRB1IE0
TMRB1FN
TMRB1CLK
TMRB1EN
RSVD
TMRA1POL
TMRA1CLR
TMRA1IE1 TMRA1IE0
TMRA1FN
TMRA1CLK
TMRA1EN
Table 842: CTRL1 Register Bits
Bit Name Reset RW Description
31 CTLINK1 0x0 RW
Counter/Timer A1/B1 Link bit.
TWO_16BIT_TIMERS = 0x0 - Use A1/B1 timers as two independent 16-bit
timers (default).
32BIT_TIMER = 0x1 - Link A1/B1 timers into a single 32-bit timer.
30:29 RSVD 0x0 RO
RESERVED