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Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 588 of 909 2019 Ambiq Micro, Inc.

13.21.2.8TMR1 Register

Counter/Timer Register

OFFSET: 0x00000020

INSTANCE 0 ADDRESS: 0x40008020

This register holds the running time or event count for ctimer 1. This is either for each 16 bit half or for the

whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks

and are completely independent.

21:16 TMRB0LMT 0x0 RW

Counter/Timer B0 Pattern Limit Count.

15 RSVD 0x0 RO

RESERVED

14 TMRA0EN23 0x0 RW

Counter/Timer A0 Upper compare enable.

DIS = 0x1 - Disable enhanced functions.

EN = 0x0 - Enable enhanced functions.

13 TMRA0POL23 0x0 RW

Counter/Timer A0 Upper output polarity

NORM = 0x0 - Upper output normal polarity

INV = 0x1 - Upper output inverted polarity.

12 TMRA0TINV 0x0 RW

Counter/Timer A0 Invert on trigger.

DIS = 0x0 - Disable invert on trigger

EN = 0x1 - Enable invert on trigger

TMRA0NO-

SYNC

0x0 RW

Source clock synchronization control.

DIS = 0x0 - Synchronization on source clock

NOSYNC = 0x1 - No synchronization on source clock

10:7 TMRA0TRIG 0x0 RW

Counter/Timer A0 Trigger Select.

DIS = 0x0 - Trigger source is disabled.

B0OUT = 0x1 - Trigger source is CTIMERB0 OUT.

B3OUT = 0x2 - Trigger source is CTIMERB3 OUT.

A3OUT = 0x3 - Trigger source is CTIMERA3 OUT.

A1OUT = 0x4 - Trigger source is CTIMERA1 OUT.

B1OUT = 0x5 - Trigger source is CTIMERB1 OUT.

A5OUT = 0x6 - Trigger source is CTIMERA5 OUT.

B5OUT = 0x7 - Trigger source is CTIMERB5 OUT.

B3OUT2 = 0x8 - Trigger source is CTIMERB3 OUT2.

A3OUT2 = 0x9 - Trigger source is CTIMERA3 OUT2.

B6OUT2 = 0xA - Trigger source is CTIMERB6 OUT2.

A2OUT2 = 0xB - Trigger source is CTIMERA2 OUT2.

A6OUT2DUAL = 0xC - Trigger source is CTIMERA6 OUT2, dual edge.

A7OUT2DUAL = 0xD - Trigger source is CTIMERA7 OUT2, dual edge.

B4OUT2DUAL = 0xE - Trigger source is CTIMERB4 OUT2, dual edge.

A4OUT2DUAL = 0xF - Trigger source is CTIMERA4 OUT2, dual edge.

6:0 TMRA0LMT 0x0 RW

Counter/Timer A0 Pattern Limit Count.

Table 834: AUX0 Register Bits

Bit Name Reset RW Description