User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 586 of 909 2019 Ambiq Micro, Inc.
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13.21.2.6CMPRAUXB0 Register
Counter/Timer B0 Compare Registers
OFFSET: 0x00000018
INSTANCE 0 ADDRESS: 0x40008018
Enhanced compare limits for timer half B. This is valid if timer 0 is set to function 4 and function 5.
13.21.2.7AUX0 Register
Counter/Timer Auxiliary
OFFSET: 0x0000001C
INSTANCE 0 ADDRESS: 0x4000801C
Control bit fields for both halves of timer 0.
Table 830: CMPRAUXA0 Register Bits
Bit Name Reset RW Description
31:16 CMPR3A0 0x0 RW
Counter/Timer A0 Compare Register 3. Holds the upper limit for timer half
A.
15:0 CMPR2A0 0x0 RW
Counter/Timer A0 Compare Register 2. Holds the lower limit for timer half A.
Table 831: CMPRAUXB0 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3B0 CMPR2B0
Table 832: CMPRAUXB0 Register Bits
Bit Name Reset RW Description
31:16 CMPR3B0 0x0 RW
Counter/Timer B0 Compare Register 3. Holds the upper limit for timer half
B.
15:0 CMPR2B0 0x0 RW
Counter/Timer B0 Compare Register 2. Holds the lower limit for timer half B.