User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 585 of 909 2019 Ambiq Micro, Inc.
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13.21.2.5CMPRAUXA0 Register
Counter/Timer A0 Compare Registers
OFFSET: 0x00000014
INSTANCE 0 ADDRESS: 0x40008014
Enhanced compare limits for timer half A. This is valid if timer 0 is set to function 4 and function 5.
5:1 TMRA0CLK 0x0 RW
Counter/Timer A0 Clock Select.
TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC_DIV4 = 0x1 - Clock source is the HFRC / 4
HFRC_DIV16 = 0x2 - Clock source is HFRC / 16
HFRC_DIV256 = 0x3 - Clock source is HFRC / 256
HFRC_DIV1024 = 0x4 - Clock source is HFRC / 1024
HFRC_DIV4K = 0x5 - Clock source is HFRC / 4096
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV128 = 0x9 - Clock source is XT / 128
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK_DIV4 = 0xF - Clock source is HCLK / 4 (note: this clock is only avail-
able when MCU is in active mode)
XT_DIV4 = 0x10 - Clock source is XT / 4
XT_DIV8 = 0x11 - Clock source is XT / 8
XT_DIV32 = 0x12 - Clock source is XT / 32
RSVD = 0x13 - Clock source is Reserved.
CTMRB0 = 0x14 - Clock source is CTIMERB0 OUT.
CTMRA1 = 0x15 - Clock source is CTIMERA1 OUT.
CTMRB1 = 0x16 - Clock source is CTIMERB1 OUT.
CTMRA2 = 0x17 - Clock source is CTIMERA2 OUT.
CTMRB2 = 0x18 - Clock source is CTIMERB2 OUT.
CTMRB3 = 0x19 - Clock source is CTIMERB3 OUT.
CTMRB4 = 0x1A - Clock source is CTIMERB4 OUT.
CTMRB5 = 0x1B - Clock source is CTIMERB5 OUT.
CTMRB6 = 0x1C - Clock source is CTIMERB6 OUT.
BUCKBLE = 0x1D - Clock source is BLE buck converter TON pulses.
BUCKB = 0x1E - Clock source is Memory buck converter TON pulses.
BUCKA = 0x1F - Clock source is CPU buck converter TON pulses.
0 TMRA0EN 0x0 RW
Counter/Timer A0 Enable bit.
DIS = 0x0 - Counter/Timer A0 Disable.
EN = 0x1 - Counter/Timer A0 Enable.
Table 829: CMPRAUXA0 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR3A0 CMPR2A0
Table 828: CTRL0 Register Bits
Bit Name Reset RW Description