User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 580 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
13.21.2CTIMER Registers
13.21.2.1TMR0 Register
Counter/Timer Register
OFFSET: 0x00000000
INSTANCE 0 ADDRESS: 0x40008000
This register holds the running time or event count for ctimer 0. This is either for each 16 bit half or for the
whole 32 bit count when the pair is linked. If the pair is not linked, they can be running on seperate clocks
and are completely independent.
13.21.2.2CMPRA0 Register
Counter/Timer A0 Compare Registers
OFFSET: 0x00000004
INSTANCE 0 ADDRESS: 0x40008004
This contains the Compare limits for timer 0 A half.
Table 821: TMR0 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CTTMRB0 CTTMRA0
Table 822: TMR0 Register Bits
Bit Name Reset RW Description
31:16 CTTMRB0 0x0 RO
Counter/Timer B0.
15:0 CTTMRA0 0x0 RO
Counter/Timer A0.
Table 823: CMPRA0 Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CMPR1A0 CMPR0A0