User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 576 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
Each timer may be clocked by one of two of the pads, selected by the REG_CTIMER_INCFG register as
shown in Table 819. The polarity of the input clock is selection by the POL23 bit.
The REG_GPIO_CTENCFG register holds one bit for each pad, which selects whether the pad is an
output (if 0) or an input (if 1).
The assignments in Table 818 and Table 819 assume that COMMON outputs will be created from either
A7OUT2 or A6OUT2. These outputs can also be used in the case where it is desired to drive multiple
outputs from the same timer.
PAD37 (7) CT29
Force
to 0
Force
to 1
B5OUT2 A1OUT A7OUT A3OUT2 A6OUT2 A7OUT2
PAD39 (2) CT25
Force
to 0
Force
to 1
B4OUT2 B2OUT A6OUT A2OUT2 A6OUT2 A7OUT2
PAD42 (2) CT16
Force
to 0
Force
to 1
A4OUT A0OUT A0OUT2 B3OUT2 A6OUT2 A7OUT2
PAD43 (2) CT18
Force
to 0
Force
to 1
B4OUT B0OUT A0OUT A3OUT2 A6OUT2 A7OUT2
PAD44 (2) CT20
Force
to 0
Force
to 1
A5OUT A1OUT A1OUT2 B2OUT2 A6OUT2 A7OUT2
PAD45 (2) CT22
Force
to 0
Force
to 1
B5OUT B1OUT A6OUT A2OUT2 A6OUT2 A7OUT2
PAD46 (2) CT24
Force
to 0
Force
to 1
A6OUT A2OUT A1OUT B1OUT2 A6OUT2 A7OUT2
PAD47 (2) CT26
Force
to 0
Force
to 1
B6OUT B2OUT A5OUT A1OUT2 A6OUT2 A7OUT2
PAD48 (2) CT28
Force
to 0
Force
to 1
A7OUTB A3OUT A5OUT2 B0OUT2 A6OUT2 A7OUT2
PAD49 (2) CT30
Force
to 0
Force
to 1
B7OUT B3OUT A4OUT2 A0OUT2 A6OUT2 A7OUT2
Table 819: CTIMER Pad Input Connections
CTIMER
INCFG
CTIMER
INCFG
0 1 0 1
CTIMERA0 CT0 CT1 CTIMERB0 CT2 CT3
CTIMERA1 CT4 CT5 CTIMERB1 CT6 CT7
CTIMERA2 CT8 CT9 CTIMERB2 CT10 CT11
CTIMERA3 CT12 CT13 CTIMERB3 CT14 CT15
CTIMERA4 CT16 CT17 CTIMERB4 CT18 CT19
CTIMERA5 CT20 CT21 CTIMERB5 CT22 CT23
CTIMERA6 CT24 CT25 CTIMERB6 CT26 CT27
CTIMERA7 CT28 CT29 CTIMERB7 CT30 CT31
Table 818: Counter/Timer Pad Configuration
Pad (FNCSEL)
ctimer
output
signal
Output Selection (REG_CTIMER_INCFG)
0 1 2 3 4 5 6 7