User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 560 of 909 2019 Ambiq Micro, Inc.
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Figure 69. Counter/Timer Operation, FN = 2
The normal interrupt is generated on the rising edge of the output (before polarity is applied) if IE0 is set,
as shown in Counter/Timer Operation, FN = 2Figure 69. The secondary interrupt is generated on the
falling edge of the output if the REG_CTIMER_TMRxyIE1 bit is set.
13.2.4 Repeated Pulse (FN = 3)
Operation in this mode is shown in Figure 70. When the Timer is enabled, the pin output is at the level
selected by the POL bit and the Timer is at zero because CLR has been asserted previously. The Timer
counts up on each selected clock, and when it reaches the value in the corresponding CMPR0 Register
the output pin switches polarity (if the PE bit is set) and an interrupt is generated (if the IE bit is set). At this
point the Timer continues to increment and the output pin is maintained at the selected level until the Timer
reaches the value in the CMPR1 Register, at which point it switches back to the original level. This allows
the creation of a pulse of a specified width. The interrupt may be cleared by writing the corresponding WC
bit in the TMRWCR Register. Note that CMPR1 must be at least 1 so that the repeat interval is two clock
cycles.
The Timer is reset to 0 and continues to increment, so that a stream of pulses of the specified width and
period is generated. If the EN bit is cleared, the Timer stops counting, but is not cleared, so the sequence
may be paused and restarted. This mode is particularly valuable for creating a PWM (Pulse Width
Modulation) output on the pin which may be used, for example, to vary the brightness of an LED.
Figure 70. Counter/Timer Operation, FN = 3
Out (POL = 0)
Out (POL = 1)
INT
Counter
EN
0 Incrementing 0
~CMPR0 + 2
~CMPR1 + 2
Out (POL = 0)
Out (POL = 1)
INT
Counter
EN
0 Incrementing 0
~CMPR0 + 2
~CMPR1 + 2
CMPR0 + 1
CMPR1 + 1
Incrementing 0 Inc