User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 554 of 909 2019 Ambiq Micro, Inc.
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12.4.2.6 INTEN Register
RTC Interrupt Register: Enable
OFFSET: 0x00000100
INSTANCE 0 ADDRESS: 0x40004300
Set bits in this register to allow this module to generate the corresponding interrupt.
12.4.2.7 INTSTAT Register
RTC Interrupt Register: Status
OFFSET: 0x00000104
INSTANCE 0 ADDRESS: 0x40004304
Read bits from this register to discover the cause of a recent interrupt.
3:1 RPT 0x0 RW
Alarm repeat interval
DIS = 0x0 - Alarm interrupt disabled
YEAR = 0x1 - Interrupt every year
MONTH = 0x2 - Interrupt every month
WEEK = 0x3 - Interrupt every week
DAY = 0x4 - Interrupt every day
HR = 0x5 - Interrupt every hour
MIN = 0x6 - Interrupt every minute
SEC = 0x7 - Interrupt every second/10th/100th
0 WRTC 0x0 RW
Counter write control
DIS = 0x0 - Counter writes are disabled
EN = 0x1 - Counter writes are enabled
Table 808: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
ALM
Table 809: INTEN Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED
0 ALM 0x0 RW
RTC Alarm interrupt
Table 807: RTCCTL Register Bits
Bit Name Reset RW Description