User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 547 of 909 2019 Ambiq Micro, Inc.
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12.3 Real Time Clock
Figure 65. Block diagram for the Real Time Clock Module
12.3.1 RTC Functional Overview
The Real Time Clock (RTC) Module, shown in Figure 65, provides an accurate real time measurement.
Key features are:
▪ 100
th
of a second resolution
▪ Time is measured for the years between 1900 and 2199
▪ Automatic leap year calculation
▪ Hours may be specified in 12 or 24 hour mode
▪ Alarm precise to 1/100 second
▪ Alarm interval every 100
th
second, 10
th
second, second, minute, hour, day, week, month or year.
▪ 100 Hz input clock taken from either the high accuracy XT Oscillator or the low power LFRC Oscillator.
12.3.2 Calendar Counters
The real time is held in a set of eight Calendar Counters, which hold the current 1/100
th
of a second
(REG_CLK_GEN_CTRLOW_CTR100), the current second (REG_CLK_GEN_CTRLOW_CTRSEC), the
minute (REG_CLK_GEN_CTRLOW_CTRMIN), the hour (REG_CLK_GEN_CTRLOW_CTRHR), the
current day of the month (REG_CLK_GEN_CTRUP_CTRDATE), the current day of the week
(REG_CLK_GEN_CTRUP_CTRWKDY), the current month (REG_CLK_GEN_CTRUP_CTRMO), the
current year (REG_CLK_GEN_CTRUP_CTRYR) and the current century (REG_CLK_GEN_CTRUP_CB),
all in BCD format. In order to insure that the RTC starts precisely, the timer chain which generates the 100
Hz clock is reset to 0 whenever any of the Calendar Counter Registers is written. Since unintentional
modification of the Calendar Counters is a serious problem, the REG_CLK_GEN_RTCCTL_WRTC bit
must be set in order to write any of the counters, and should be reset by software after any load of the
Calendar Counters.
Software may stop the clock to the Calendar Counters by setting the REG_CLK_GEN_RTCCTL_RSTOP
bit. This may be used in modes like Stopwatch to precisely start and stop the Calendar Counters.
12.3.3 Calendar Counter Reads
The RTC includes special logic to help insure that the Calendar Counters may be read reliably, i.e. that no
rollover has occurred. Because two 32-bit reads are required to read the complete set of counters, it is
possible that a delay occurs between the two reads which causes a rollover to occur. An interrupt is the
most likely reason this could occur. If two 100 Hz clocks occur between these two reads, the
REG_CLK_GEN_CTRUP_CTRERR bit will be set. Software should check this bit after any Calendar
Counter read, and perform the read again if it is set. Any read of the upper counter word will clear the
CTRERR bit.
100ths
Ctr
100Hz
Secs
Ctr
Mins
Ctr
Hours
Ctr
Date
Ctr
Month
Ctr
Year
Ctr
Wkdy
Ctr
100ths
Alm
Secs
Alm
Mins
Alm
Hours
Alm
Date
Alm
Month
Alm
Wkdy
Alm
Cmpr Cmpr Cmpr Cmpr Cmpr Cmpr Cmpr
Int
Logic