User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 541 of 909 2019 Ambiq Micro, Inc.
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12.2.2.13FREQCTRL Register
HFRC Frequency Control register
OFFSET: 0x00000034
INSTANCE 0 ADDRESS: 0x40004034
This register provides the burst control and burst status.
Table 783: CLOCKEN3STAT Register Bits
Bit Name Reset RW Description
31:0
CLOCK-
EN3STAT
0x0 RO
Clock enable status 3
DAP_enabled = 0x20000 - DAP clock is enabled [17]
VCOMP_enabled = 0x40000 - VCOMP powerdown indicator [18]
XTAL_enabled = 0x1000000 - XTAL is enabled [24]
HFRC_enabled = 0x2000000 - HFRC is enabled [25]
HFADJEN = 0x4000000 - HFRC Adjust enabled [26]
HFRC_en_out = 0x8000000 - HFRC Enabled out [27]
RTC_XT = 0x10000000 - RTC use XT [28]
clkout_xtal_en = 0x20000000 - XTAL clkout enabled [29]
clkout_hfrc_en = 0x40000000 - HFRC clkout enabled [30]
flashclk_en = 0x80000000 - Flash clk is enabled [31]
Table 784: FREQCTRL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
BURSTSTATUS
BURSTACK
BURSTREQ
Table 785: FREQCTRL Register Bits
Bit Name Reset RW Description
31:3 RSVD 0x0 RO
RESERVED
2 BURSTSTATUS 0x0 RO
This represents frequency burst status.
1 BURSTACK 0x0 RO
Frequency Burst Request Acknowledge. Frequency burst requested is
always acknowledged whether burst is granted or not depending on feature
enable.
0BURSTREQ 0x0RW
Frequency Burst Enable Request
DIS = 0x0 - Frequency for ARM core stays at 48MHz
EN = 0x1 - Frequency for ARM core is increased to 96MHz