User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 540 of 909 2019 Ambiq Micro, Inc.
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12.2.2.12CLOCKEN3STAT Register
Clock Enable Status
OFFSET: 0x00000030
INSTANCE 0 ADDRESS: 0x40004030
This is a continuation of the clock enable status.
Table 781: CLOCKEN2STAT Register Bits
Bit Name Reset RW Description
31:0
CLOCK-
EN2STAT
0x0 RO
Clock enable status 2
IOMSTRIFC1_CLKEN = 0x1 - Clock enable for the IO MASTER 1 IFC
INTERFACE
IOMSTRIFC2_CLKEN = 0x2 - Clock enable for the IO MASTER 2 IFC
INTERFACE
IOMSTRIFC3_CLKEN = 0x4 - Clock enable for the IO MASTER 3 IFC
INTERFACE
IOMSTRIFC4_CLKEN = 0x8 - Clock enable for the IO MASTER 4 IFC
INTERFACE
IOMSTRIFC5_CLKEN = 0x10 - Clock enable for the IO MASTER 5 IFC
INTERFACE
PDM_CLKEN = 0x20 - Clock enable for the PDM
PDMIFC_CLKEN = 0x40 - Clock enable for the PDM INTERFACE
PWRCTRL_CLKEN = 0x80 - Clock enable for the PWRCTRL
PWRCTRL_COUNT_CLKEN = 0x100 - Clock enable for the PWRCTRL
counter
RSTGEN_CLKEN = 0x200 - Clock enable for the RSTGEN
SCARD_CLKEN = 0x400 - Clock enable for the SCARD
SCARD_ALTAPB_CLKEN = 0x800 - Clock enable for the SCARD ALTAPB
STIMER_CNT_CLKEN = 0x1000 - Clock enable for the STIMER_CNT_-
CLKEN
TPIU_CLKEN = 0x2000 - Clock enable for the TPIU_CLKEN
UART0HF_CLKEN = 0x4000 - Clock enable for the UART0 HF
UART1HF_CLKEN = 0x8000 - Clock enable for the UART1 HF
WDT_CLKEN = 0x8000 - Clock enable for the Watchdog timer
XT_32KHZ_EN = 0x40000000 - Clock enable for the XT 32KHZ
FORCEHFRC = 0x80000000 - HFRC is forced on Status.
Table 782: CLOCKEN3STAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CLOCKEN3STAT