User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 537 of 909 2019 Ambiq Micro, Inc.
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INSTANCE 0 ADDRESS: 0x4000401C
This register provides status to the XT oscillator and the source of the RTC.
12.2.2.9 HFADJ Register
HFRC Adjustment
OFFSET: 0x00000020
INSTANCE 0 ADDRESS: 0x40004020
This register controls the HFRC adjustment. The HFRC clock can change with temperature and process
corners, and this register controls the HFRC adjustment logic which reduces the fluctuations to the clock.
Table 774: STATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
OSCF
OMODE
Table 775: STATUS Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED
1OSCF 0x0RO
XT Oscillator is enabled but not oscillating
0OMODE 0x0RO
Current RTC oscillator (1 => LFRC, 0 => XT). After an RTC oscillator
change, it may take up to 2 seconds for this field to reflect the new oscillator.
Table 776: HFADJ Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
HFADJGAIN
HFWARMUP
HFXTADJ RSVD
HFADJCK
HFADJEN
Table 777: HFADJ Register Bits
Bit Name Reset RW Description
31:24 RSVD 0x0 RO
RESERVED