User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 536 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
12.2.2.7 CCTRL Register
HFRC Clock Control
OFFSET: 0x00000018
INSTANCE 0 ADDRESS: 0x40004018
This register controls the main divider for HFRC clock. If this is set, all internal HFRC clock sources are
divided by 2.
12.2.2.8 STATUS Register
Clock Generator Status
OFFSET: 0x0000001C
Table 770: CLKKEY Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CLKKEY
Table 771: CLKKEY Register Bits
Bit Name Reset RW Description
31:0 CLKKEY 0x0 RW
Key register value.
Key = 0x47 - Key
Table 772: CCTRL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CORE-
Table 773: CCTRL Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
RESERVED
0 CORESEL 0x1 RW
Core Clock divisor
HFRC = 0x0 - Core Clock is HFRC
HFRC_DIV2 = 0x1 - Core Clock is HFRC / 2