User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 535 of 909 2019 Ambiq Micro, Inc.
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12.2.2.6 CLKKEY Register
Key Register for Clock Control Register
OFFSET: 0x00000014
INSTANCE 0 ADDRESS: 0x40004014
Key Register for Clock Control Register
5:0 CKSEL 0x0 RW
CLKOUT signal select
LFRC = 0x0 - LFRC
XT_DIV2 = 0x1 - XT / 2
XT_DIV4 = 0x2 - XT / 4
XT_DIV8 = 0x3 - XT / 8
XT_DIV16 = 0x4 - XT / 16
XT_DIV32 = 0x5 - XT / 32
RTC_1Hz = 0x10 - 1 Hz as selected in RTC
XT_DIV2M = 0x16 - XT / 2^21
XT = 0x17 - XT
CG_100Hz = 0x18 - 100 Hz as selected in CLKGEN
LFRC_DIV2 = 0x23 - LFRC / 2
LFRC_DIV32 = 0x24 - LFRC / 32
LFRC_DIV512 = 0x25 - LFRC / 512
LFRC_DIV32K = 0x26 - LFRC / 32768
XT_DIV256 = 0x27 - XT / 256
XT_DIV8K = 0x28 - XT / 8192
XT_DIV64K = 0x29 - XT / 2^16
ULFRC_DIV16 = 0x2A - Uncal LFRC / 16
ULFRC_DIV128 = 0x2B - Uncal LFRC / 128
ULFRC_1Hz = 0x2C - Uncal LFRC / 1024
ULFRC_DIV4K = 0x2D - Uncal LFRC / 4096
ULFRC_DIV1M = 0x2E - Uncal LFRC / 2^20
LFRC_DIV1M = 0x31 - LFRC / 2^20
XTNE = 0x35 - XT (not autoenabled)
XTNE_DIV16 = 0x36 - XT / 16 (not autoenabled)
LFRCNE_DIV32 = 0x37 - LFRC / 32 (not autoenabled)
LFRCNE = 0x39 - LFRC (not autoenabled) - Default for undefined values
Table 769: CLKOUT Register Bits
Bit Name Reset RW Description