User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 532 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
12.2.2.3 ACALCTR Register
Autocalibration Counter
OFFSET: 0x00000008
INSTANCE 0 ADDRESS: 0x40004008
This register can be used for 2 purposes. The first is to calibrate the LFRC clock using the XT clock
source. The second is to measure an internal clock signal relative to the external clock. In that case, the
ACALCTR will show the multiple of the external clock with respect to the internal clock signal. E.g. Fref =
Fmeas x ACALCTR. Note that this register should not be confused with the HFRC Adjustment register,
which is separately defined in CLKGEN_HFADJ register.
Table 762: CALRC Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CALRC
Table 763: CALRC Register Bits
Bit Name Reset RW Description
31:18 RSVD 0x0 RO
RESERVED
17:0 CALRC 0x0 RW
LFRC Oscillator calibration value. This register will enable the hardware to
increase or decrease the number of cycles in a 512 Hz clock derived from
the original 1024 version. The most significant bit is the sign. A '1' is a
reduction, and a '0' is an addition. This calibration value will add or reduce
the number of cycles programmed here across a 32 second interval. The
range is from -131072 (decimal) to 131071 (decimal). This register is nor-
mally used in conjuction with ACALCTR register. The CALRC register will
load the ACALCTR register (bits 17:0) if the ACALCTR register is set to
measure the LFRC with the XT clock.
Table 764: ACALCTR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD ACALCTR
Table 765: ACALCTR Register Bits
Bit Name Reset RW Description
31:24 RSVD 0x0 RO
RESERVED