User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 529 of 909 2019 Ambiq Micro, Inc.
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12.1.8 Generating 100 Hz
The Real Time Clock (RTC) module requires a 100 Hz clock which is provided by the Clock Generator.
This clock may come either from the LFRC or the XT Oscillators, as determined by the
REG_CLKGEN_OCTRL_OSEL bit. Since 100 Hz is not a simple power of two division of either of these
oscillators, special functions are used to create it.
If the XT Oscillator is selected, 100 Hz is generated by dividing the 2048 Hz division of the XT by 21 for 12
iterations and by 20 for 13 iterations out of every 25 clock periods. This produces an effective division of:
(21 * 12 + 20 * 13)/25 = 20.48
producing an exact average frequency of 100 Hz with a maximum jitter of less than 1 ms.
If the LFRC Oscillator is selected, 100 Hz is generated by dividing the 256 Hz division of the LFRC by 2 for
11 iterations and by 3 for 14 iterations out of every 25 clock periods. This produces an effective division of:
(2 * 11 + 3 * 14)/25 = 2.56
producing an exact average frequency of 100 Hz with a maximum jitter of less than 8 ms.
12.2 CLKGEN Registers
Clock Generator
INSTANCE 0 BASE ADDRESS:0x40004000
This is the register bank for the clock generator registers. It includes the RTC unit and the register control
for BLE Ton Adjust unit