User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 509 of 909 2019 Ambiq Micro, Inc.
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11.7.2.60INT0EN Register
GPIO Interrupt Registers 31-0: Enable
OFFSET: 0x00000200
INSTANCE 0 ADDRESS: 0x40010200
Set bits in this register to allow this module to generate the corresponding interrupt.
8EN8 0x1RW
CT8 Enable
DIS = 0x1 - Disable CT8 for output
EN = 0x0 - Enable CT8 for output
7EN7 0x1RW
CT7 Enable
DIS = 0x1 - Disable CT7 for output
EN = 0x0 - Enable CT7 for output
6EN6 0x1RW
CT6 Enable
DIS = 0x1 - Disable CT6 for output
EN = 0x0 - Enable CT6 for output
5EN5 0x1RW
CT5 Enable
DIS = 0x1 - Disable CT5 for output
EN = 0x0 - Enable CT5 for output
4EN4 0x1RW
CT4 Enable
DIS = 0x1 - Disable CT4 for output
EN = 0x0 - Enable CT4 for output
3EN3 0x1RW
CT3 Enable
DIS = 0x1 - Disable CT3 for output
EN = 0x0 - Enable CT3 for output
2EN2 0x1RW
CT2 Enable
DIS = 0x1 - Disable CT2 for output
EN = 0x0 - Enable CT2 for output
1EN1 0x1RW
CT1 Enable
DIS = 0x1 - Disable CT1 for output
EN = 0x0 - Enable CT1 for output
0EN0 0x1RW
CT0 Enable
DIS = 0x1 - Disable CT0 for output
EN = 0x0 - Enable CT0 for output
Table 742: CTENCFG Register Bits
Bit Name Reset RW Description