User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 508 of 909 2019 Ambiq Micro, Inc.
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21 EN21 0x1 RW
CT21 Enable
DIS = 0x1 - Disable CT21 for output
EN = 0x0 - Enable CT21 for output
20 EN20 0x1 RW
CT20 Enable
DIS = 0x1 - Disable CT20 for output
EN = 0x0 - Enable CT20 for output
19 EN19 0x1 RW
CT19 Enable
DIS = 0x1 - Disable CT19 for output
EN = 0x0 - Enable CT19 for output
18 EN18 0x1 RW
CT18 Enable
DIS = 0x1 - Disable CT18 for output
EN = 0x0 - Enable CT18 for output
17 EN17 0x1 RW
CT17 Enable
DIS = 0x1 - Disable CT17 for output
EN = 0x0 - Enable CT17 for output
16 EN16 0x1 RW
CT16 Enable
DIS = 0x1 - Disable CT16 for output
EN = 0x0 - Enable CT16 for output
15 EN15 0x1 RW
CT15 Enable
DIS = 0x1 - Disable CT15 for output
EN = 0x0 - Enable CT15 for output
14 EN14 0x1 RW
CT14 Enable
DIS = 0x1 - Disable CT14 for output
EN = 0x0 - Enable CT14 for output
13 EN13 0x1 RW
CT13 Enable
DIS = 0x1 - Disable CT13 for output
EN = 0x0 - Enable CT13 for output
12 EN12 0x1 RW
CT12 Enable
DIS = 0x1 - Disable CT12 for output
EN = 0x0 - Enable CT12 for output
11 EN11 0x1 RW
CT11 Enable
DIS = 0x1 - Disable CT11 for output
EN = 0x0 - Enable CT11 for output
10 EN10 0x1 RW
CT10 Enable
DIS = 0x1 - Disable CT10 for output
EN = 0x0 - Enable CT10 for output
9EN9 0x1RW
CT9 Enable
DIS = 0x0 - Disable CT9 for output
EN = 0x0 - Enable CT9 for output
Table 742: CTENCFG Register Bits
Bit Name Reset RW Description