User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 505 of 909 2019 Ambiq Micro, Inc.
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11.7.2.57ALTPADCFGM Register
Alternate Pad Configuration reg12 (Pads 49,48)
OFFSET: 0x00000110
INSTANCE 0 ADDRESS: 0x40010110
This register has additional configuration control for pads 49, 48
15:13 RSVD 0x0 RO
RESERVED
12 PAD45_SR 0x0 RW
Pad 45 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD45_DS1 0x0 RW
Pad 45 high order drive strength selection. Used in conjunction with
PAD45STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD44_SR 0x0 RW
Pad 44 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD44_DS1 0x0 RW
Pad 44 high order drive strength selection. Used in conjunction with
PAD44STRNG field to set the pad drive strength.
Table 737: ALTPADCFGM Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD49_SR
RSVD
PAD49_DS1
RSVD
PAD48_SR
RSVD
PAD48_DS1
Table 738: ALTPADCFGM Register Bits
Bit Name Reset RW Description
31:13 RSVD 0x0 RO
RESERVED
12 PAD49_SR 0x0 RW
Pad 49 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
Table 736: ALTPADCFGL Register Bits
Bit Name Reset RW Description