User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 504 of 909 2019 Ambiq Micro, Inc.
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11.7.2.56ALTPADCFGL Register
Alternate Pad Configuration reg11 (Pads 47,46,45,44)
OFFSET: 0x0000010C
INSTANCE 0 ADDRESS: 0x4001010C
This register has additional configuration control for pads 47, 46, 45, 44
3:1 RSVD 0x0 RO
RESERVED
0 PAD40_DS1 0x0 RW
Pad 40 high order drive strength selection. Used in conjunction with
PAD40STRNG field to set the pad drive strength.
Table 735: ALTPADCFGL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD47_SR
RSVD
PAD47_DS1
RSVD
PAD46_SR
RSVD
PAD46_DS1
RSVD
PAD45_SR
RSVD
PAD45_DS1
RSVD
PAD44_SR
RSVD
PAD44_DS1
Table 736: ALTPADCFGL Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD47_SR 0x0 RW
Pad 47 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
27:25 RSVD 0x0 RO
RESERVED
24 PAD47_DS1 0x0 RW
Pad 47 high order drive strength selection. Used in conjunction with
PAD47STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD46_SR 0x0 RW
Pad 46 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD46_DS1 0x0 RW
Pad 46 high order drive strength selection. Used in conjunction with
PAD46STRNG field to set the pad drive strength.
Table 734: ALTPADCFGK Register Bits
Bit Name Reset RW Description