User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 502 of 909 2019 Ambiq Micro, Inc.
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11.7.2.55ALTPADCFGK Register
Alternate Pad Configuration reg10 (Pads 43,42,41,40)
OFFSET: 0x00000108
INSTANCE 0 ADDRESS: 0x40010108
This register has additional configuration control for pads 43, 42, 41, 40
27:25 RSVD 0x0 RO
RESERVED
24 PAD39_DS1 0x0 RW
Pad 39 high order drive strength selection. Used in conjunction with
PAD39STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD38_SR 0x0 RW
Pad 38 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD38_DS1 0x0 RW
Pad 38 high order drive strength selection. Used in conjunction with
PAD38STRNG field to set the pad drive strength.
15:13 RSVD 0x0 RO
RESERVED
12 PAD37_SR 0x0 RW
Pad 37 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD37_DS1 0x0 RW
Pad 37 high order drive strength selection. Used in conjunction with
PAD37STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD36_SR 0x0 RW
Pad 36 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD36_DS1 0x0 RW
Pad 36 high order drive strength selection. Used in conjunction with
PAD36STRNG field to set the pad drive strength.
Table 732: ALTPADCFGJ Register Bits
Bit Name Reset RW Description