User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 501 of 909 2019 Ambiq Micro, Inc.
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11.7.2.54ALTPADCFGJ Register
Alternate Pad Configuration reg9 (Pads 39,38,37,36)
OFFSET: 0x00000104
INSTANCE 0 ADDRESS: 0x40010104
This register has additional configuration control for pads 39, 38, 37, 36
15:13 RSVD 0x0 RO
RESERVED
12 PAD33_SR 0x0 RW
Pad 33 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD33_DS1 0x0 RW
Pad 33 high order drive strength selection. Used in conjunction with
PAD33STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD32_SR 0x0 RW
Pad 32 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD32_DS1 0x0 RW
Pad 32 high order drive strength selection. Used in conjunction with
PAD32STRNG field to set the pad drive strength.
Table 731: ALTPADCFGJ Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD39_SR
RSVD
PAD39_DS1
RSVD
PAD38_SR
RSVD
PAD38_DS1
RSVD
PAD37_SR
RSVD
PAD37_DS1
RSVD
PAD36_SR
RSVD
PAD36_DS1
Table 732: ALTPADCFGJ Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD39_SR 0x0 RW
Pad 39 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
Table 730: ALTPADCFGI Register Bits
Bit Name Reset RW Description