User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 500 of 909 2019 Ambiq Micro, Inc.
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11.7.2.53ALTPADCFGI Register
Alternate Pad Configuration reg8 (Pads 35,34,33,32)
OFFSET: 0x00000100
INSTANCE 0 ADDRESS: 0x40010100
This register has additional configuration control for pads 35, 34, 33, 32
3:1 RSVD 0x0 RO
RESERVED
0 PAD28_DS1 0x0 RW
Pad 28 high order drive strength selection. Used in conjunction with
PAD28STRNG field to set the pad drive strength.
Table 729: ALTPADCFGI Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD35_SR
RSVD
PAD35_DS1
RSVD
PAD34_SR
RSVD
PAD34_DS1
RSVD
PAD33_SR
RSVD
PAD33_DS1
RSVD
PAD32_SR
RSVD
PAD32_DS1
Table 730: ALTPADCFGI Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD35_SR 0x0 RW
Pad 35 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
27:25 RSVD 0x0 RO
RESERVED
24 PAD35_DS1 0x0 RW
Pad 35 high order drive strength selection. Used in conjunction with
PAD35STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD34_SR 0x0 RW
Pad 34 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD34_DS1 0x0 RW
Pad 34 high order drive strength selection. Used in conjunction with
PAD34STRNG field to set the pad drive strength.
Table 728: ALTPADCFGH Register Bits
Bit Name Reset RW Description