User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 498 of 909 2019 Ambiq Micro, Inc.
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11.7.2.52ALTPADCFGH Register
Alternate Pad Configuration reg7 (Pads 31,30,29,28)
OFFSET: 0x000000FC
INSTANCE 0 ADDRESS: 0x400100FC
This register has additional configuration control for pads 31, 30, 29, 28
27:25 RSVD 0x0 RO
RESERVED
24 PAD27_DS1 0x0 RW
Pad 27 high order drive strength selection. Used in conjunction with
PAD27STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD26_SR 0x0 RW
Pad 26 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD26_DS1 0x0 RW
Pad 26 high order drive strength selection. Used in conjunction with
PAD26STRNG field to set the pad drive strength.
15:13 RSVD 0x0 RO
RESERVED
12 PAD25_SR 0x0 RW
Pad 25 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD25_DS1 0x0 RW
Pad 25 high order drive strength selection. Used in conjunction with
PAD25STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD24_SR 0x0 RW
Pad 24 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD24_DS1 0x0 RW
Pad 24 high order drive strength selection. Used in conjunction with
PAD24STRNG field to set the pad drive strength.
Table 726: ALTPADCFGG Register Bits
Bit Name Reset RW Description