User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 497 of 909 2019 Ambiq Micro, Inc.
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11.7.2.51ALTPADCFGG Register
Alternate Pad Configuration reg6 (Pads 27,26,25,24)
OFFSET: 0x000000F8
INSTANCE 0 ADDRESS: 0x400100F8
This register has additional configuration control for pads 27, 26, 25, 24
15:13 RSVD 0x0 RO
RESERVED
12 PAD21_SR 0x0 RW
Pad 21 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD21_DS1 0x0 RW
Pad 21 high order drive strength selection. Used in conjunction with
PAD21STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD20_SR 0x0 RW
Pad 20 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD20_DS1 0x0 RW
Pad 20 high order drive strength selection. Used in conjunction with
PAD20STRNG field to set the pad drive strength.
Table 725: ALTPADCFGG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD27_SR
RSVD
PAD27_DS1
RSVD
PAD26_SR
RSVD
PAD26_DS1
RSVD
PAD25_SR
RSVD
PAD25_DS1
RSVD
PAD24_SR
RSVD
PAD24_DS1
Table 726: ALTPADCFGG Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD27_SR 0x0 RW
Pad 27 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
Table 724: ALTPADCFGF Register Bits
Bit Name Reset RW Description