User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 496 of 909 2019 Ambiq Micro, Inc.
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11.7.2.50ALTPADCFGF Register
Alternate Pad Configuration reg5 (Pads 23,22,21,20)
OFFSET: 0x000000F4
INSTANCE 0 ADDRESS: 0x400100F4
This register has additional configuration control for pads 23, 22, 21, 20
3:1 RSVD 0x0 RO
RESERVED
0 PAD16_DS1 0x0 RW
Pad 16 high order drive strength selection. Used in conjunction with
PAD16STRNG field to set the pad drive strength.
Table 723: ALTPADCFGF Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD23_SR
RSVD
PAD23_DS1
RSVD
PAD22_SR
RSVD
PAD22_DS1
RSVD
PAD21_SR
RSVD
PAD21_DS1
RSVD
PAD20_SR
RSVD
PAD20_DS1
Table 724: ALTPADCFGF Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD23_SR 0x0 RW
Pad 23 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
27:25 RSVD 0x0 RO
RESERVED
24 PAD23_DS1 0x0 RW
Pad 23 high order drive strength selection. Used in conjunction with
PAD23STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD22_SR 0x0 RW
Pad 22 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD22_DS1 0x0 RW
Pad 22 high order drive strength selection. Used in conjunction with
PAD22STRNG field to set the pad drive strength.
Table 722: ALTPADCFGE Register Bits
Bit Name Reset RW Description