User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 494 of 909 2019 Ambiq Micro, Inc.
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11.7.2.49ALTPADCFGE Register
Alternate Pad Configuration reg4 (Pads 19,18,17,16)
OFFSET: 0x000000F0
INSTANCE 0 ADDRESS: 0x400100F0
This register has additional configuration control for pads 19, 18, 17, 16
27:25 RSVD 0x0 RO
RESERVED
24 PAD15_DS1 0x0 RW
Pad 15 high order drive strength selection. Used in conjunction with
PAD15STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD14_SR 0x0 RW
Pad 14 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD14_DS1 0x0 RW
Pad 14 high order drive strength selection. Used in conjunction with
PAD14STRNG field to set the pad drive strength.
15:13 RSVD 0x0 RO
RESERVED
12 PAD13_SR 0x0 RW
Pad 13 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD13_DS1 0x0 RW
Pad 13 high order drive strength selection. Used in conjunction with
PAD13STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD12_SR 0x0 RW
Pad 12 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD12_DS1 0x0 RW
Pad 12 high order drive strength selection. Used in conjunction with
PAD12STRNG field to set the pad drive strength.
Table 720: ALTPADCFGD Register Bits
Bit Name Reset RW Description