User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 493 of 909 2019 Ambiq Micro, Inc.
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11.7.2.48ALTPADCFGD Register
Alternate Pad Configuration reg3 (Pads 15,14,13,12)
OFFSET: 0x000000EC
INSTANCE 0 ADDRESS: 0x400100EC
This register has additional configuration control for pads 15, 14, 13, 12
15:13 RSVD 0x0 RO
RESERVED
12 PAD9_SR 0x0 RW
Pad 9 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD9_DS1 0x0 RW
Pad 9 high order drive strength selection. Used in conjunction with
PAD9STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD8_SR 0x0 RW
Pad 8 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD8_DS1 0x0 RW
Pad 8 high order drive strength selection. Used in conjunction with
PAD8STRNG field to set the pad drive strength.
Table 719: ALTPADCFGD Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD15_SR
RSVD
PAD15_DS1
RSVD
PAD14_SR
RSVD
PAD14_DS1
RSVD
PAD13_SR
RSVD
PAD13_DS1
RSVD
PAD12_SR
RSVD
PAD12_DS1
Table 720: ALTPADCFGD Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD15_SR 0x0 RW
Pad 15 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
Table 718: ALTPADCFGC Register Bits
Bit Name Reset RW Description