User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 492 of 909 2019 Ambiq Micro, Inc.
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11.7.2.47ALTPADCFGC Register
Alternate Pad Configuration reg2 (Pads 11,10,9,8)
OFFSET: 0x000000E8
INSTANCE 0 ADDRESS: 0x400100E8
This register has additional configuration control for pads 11, 10, 9, 8
3:1 RSVD 0x0 RO
RESERVED
0 PAD4_DS1 0x0 RW
Pad 4 high order drive strength selection. Used in conjunction with
PAD4STRNG field to set the pad drive strength.
Table 717: ALTPADCFGC Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD11_SR
RSVD
PAD11_DS1
RSVD
PAD10_SR
RSVD
PAD10_DS1
RSVD
PAD9_SR
RSVD
PAD9_DS1
RSVD
PAD8_SR
RSVD
PAD8_DS1
Table 718: ALTPADCFGC Register Bits
Bit Name Reset RW Description
31:29 RSVD 0x0 RO
RESERVED
28 PAD11_SR 0x0 RW
Pad 11 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
27:25 RSVD 0x0 RO
RESERVED
24 PAD11_DS1 0x0 RW
Pad 11 high order drive strength selection. Used in conjunction with
PAD11STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD10_SR 0x0 RW
Pad 10 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD10_DS1 0x0 RW
Pad 10 high order drive strength selection. Used in conjunction with
PAD10STRNG field to set the pad drive strength.
Table 716: ALTPADCFGB Register Bits
Bit Name Reset RW Description