User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 490 of 909 2019 Ambiq Micro, Inc.
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11.7.2.46ALTPADCFGB Register
Alternate Pad Configuration reg1 (Pads 7,6,5,4)
OFFSET: 0x000000E4
INSTANCE 0 ADDRESS: 0x400100E4
This register has additional configuration control for pads 7, 6, 5, 4
28 PAD3_SR 0x0 RW
Pad 3 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
27:25 RSVD 0x0 RO
RESERVED
24 PAD3_DS1 0x0 RW
Pad 3 high order drive strength selection. Used in conjunction with
PAD3STRNG field to set the pad drive strength.
23:21 RSVD 0x0 RO
RESERVED
20 PAD2_SR 0x0 RW
Pad 2 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
19:17 RSVD 0x0 RO
RESERVED
16 PAD2_DS1 0x0 RW
Pad 2 high order drive strength selection. Used in conjunction with
PAD2STRNG field to set the pad drive strength.
15:13 RSVD 0x0 RO
RESERVED
12 PAD1_SR 0x0 RW
Pad 1 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
11:9 RSVD 0x0 RO
RESERVED
8 PAD1_DS1 0x0 RW
Pad 1 high order drive strength selection. Used in conjunction with
PAD1STRNG field to set the pad drive strength.
7:5 RSVD 0x0 RO
RESERVED
4 PAD0_SR 0x0 RW
Pad 0 slew rate selection.
SR_EN = 0x1 - Enables Slew rate control on pad
3:1 RSVD 0x0 RO
RESERVED
0 PAD0_DS1 0x0 RW
Pad 0 high order drive strength selection. Used in conjunction with
PAD0STRNG field to set the pad drive strength.
Table 714: ALTPADCFGA Register Bits
Bit Name Reset RW Description