User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 447 of 909 2019 Ambiq Micro, Inc.
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This register controls the pad configuration controls for PAD49 through PAD48. Writes to this register must
be unlocked by the PADKEY register.
Table 649: PADREGM Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD49RSEL
PAD49FNC-
SEL
PAD49STRNG
PAD49INPEN
PAD49PULL
PAD48RSEL
PAD48FNC-
SEL
PAD48STRNG
PAD48INPEN
PAD48PULL
Table 650: PADREGM Register Bits
Bit Name Reset RW Description
31:16 RSVD 0x0 RO
RESERVED
15:14 PAD49RSEL 0x0 RW
Pad 49 pullup resistor selection.
PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
PULL6K = 0x1 - Pullup is ~6 KOhms
PULL12K = 0x2 - Pullup is ~12 KOhms
PULL24K = 0x3 - Pullup is ~24 KOhms
13:11 PAD49FNCSEL 0x3 RW
Pad 49 function select
UART0RX = 0x0 - Configure as the UART0 RX input signal
NCE49 = 0x1 - IOM/MSPPI nCE group 49
CT30 = 0x2 - CTIMER connection 30
GPIO49 = 0x3 - Configure as GPIO49
M5SDAWIR3 = 0x4 - Configure as the IOMSTR5 I2C SDA or SPI WIR3 sig-
nal
M5MISO = 0x5 - Configure as the IOMSTR5 SPI MISO input signal
RSVD6 = 0x6 - Reserved
RSVD7 = 0x7 - Reserved
10 PAD49STRNG 0x0 RW
Pad 49 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
9 PAD49INPEN 0x0 RW
Pad 49 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
8 PAD49PULL 0x0 RW
Pad 49 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled