User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 446 of 909 2019 Ambiq Micro, Inc.
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11.7.2.13PADREGM Register
Pad Configuration Register M (Pads 47-48)
OFFSET: 0x00000030
INSTANCE 0 ADDRESS: 0x40010030
13:11 PAD45FNCSEL 0x3 RW
Pad 45 function select
UA1CTS = 0x0 - Configure as the UART1 CTS input signal
NCE45 = 0x1 - IOM/MSPI nCE group 45
CT22 = 0x2 - CTIMER connection 22
GPIO45 = 0x3 - Configure as GPIO45
I2SDAT = 0x4 - I2S serial data output
PDMDATA = 0x5 - PDM serial data input
UART0RX = 0x6 - Configure as the SPI channel 5 nCE signal from IOM-
STR5
SWO = 0x7 - Configure as the serial wire debug SWO signal
10 PAD45STRNG 0x0 RW
Pad 45 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
9 PAD45INPEN 0x0 RW
Pad 45 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
8 PAD45PULL 0x0 RW
Pad 45 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
7:6 RSVD 0x0 RO
RESERVED
5:3 PAD44FNCSEL 0x3 RW
Pad 44 function select
UA1RTS = 0x0 - Configure as the UART1 RTS output signal
NCE44 = 0x1 - IOM/MSPI nCE group 44
CT20 = 0x2 - CTIMER connection 20
GPIO44 = 0x3 - Configure as GPIO44
RSVD4 = 0x4 - Reserved
M4MOSI = 0x5 - Configure as the IOMSTR4 SPI MOSI signal
M5nCE6 = 0x6 - Configure as the SPI channel 6 nCE signal from IOMSTR5
RSVD = 0x7 - Reserved
2 PAD44STRNG 0x0 RW
Pad 44 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD44INPEN 0x0 RW
Pad 44 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD44PULL 0x0 RW
Pad 44 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 648: PADREGL Register Bits
Bit Name Reset RW Description