User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 445 of 909 2019 Ambiq Micro, Inc.
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Table 648: PADREGL Register Bits
Bit Name Reset RW Description
31:30 RSVD 0x0 RO
RESERVED
29:27 PAD47FNCSEL 0x3 RW
Pad 47 function select
32kHzXT = 0x0 - Configure as the 32kHz output clock from the crystal
NCE47 = 0x1 - IOM/MSPI nCE group 47
CT26 = 0x2 - CTIMER connection 26
GPIO47 = 0x3 - Configure as GPIO47
RSVD4 = 0x4 - Reserved
M5MOSI = 0x5 - Configure as the IOMSTR5 SPI MOSI output signal
UART1RX = 0x6 - Configure as the UART1 RX input signal
RSVD7 = 0x7 - Reserved
26 PAD47STRNG 0x0 RW
Pad 47 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
25 PAD47INPEN 0x0 RW
Pad 47 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
24 PAD47PULL 0x0 RW
Pad 47 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
23:22 RSVD 0x0 RO
RESERVED
21:19 PAD46FNCSEL 0x3 RW
Pad 46 function select
32khz_XT = 0x0 - Configure as the 32kHz output clock from the crystal
NCE46 = 0x1 - IOM/MSPI nCE group 46
CT24 = 0x2 - CTIMER connection 24
GPIO46 = 0x3 - Configure as GPIO46
SCCRST = 0x4 - SCARD reset output
PDMCLK = 0x5 - PDM serial clock output
UART1TX = 0x6 - Configure as the UART1 TX output signal
SWO = 0x7 - Configure as the serial wire debug SWO signal
18 PAD46STRNG 0x0 RW
Pad 46 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
17 PAD46INPEN 0x0 RW
Pad 46 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
16 PAD46PULL 0x0 RW
Pad 46 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
15:14 RSVD 0x0 RO
RESERVED