User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 444 of 909 2019 Ambiq Micro, Inc.
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11.7.2.12PADREGL Register
Pad Configuration Register L (Pads 44-47)
OFFSET: 0x0000002C
INSTANCE 0 ADDRESS: 0x4001002C
This register controls the pad configuration controls for PAD47 through PAD44. Writes to this register must
be unlocked by the PADKEY register.
7:6 PAD40RSEL 0x0 RW
Pad 40 pullup resistor selection.
PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
PULL6K = 0x1 - Pullup is ~6 KOhms
PULL12K = 0x2 - Pullup is ~12 KOhms
PULL24K = 0x3 - Pullup is ~24 KOhms
5:3 PAD40FNCSEL 0x3 RW
Pad 40 function select
UART0RX = 0x0 - Configure as the UART0 RX input signal
UART1RX = 0x1 - Configure as the UART1 RX input signal
TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal
GPIO40 = 0x3 - Configure as GPIO40
M4SDAWIR3 = 0x4 - Configure as the IOMSTR4 I2C SDA or SPI WIR3 sig-
nal
M4MISO = 0x5 - Configure as the IOMSTR4 SPI MISO input signal
RSVD6 = 0x6 - Reserved
RSVD7 = 0x7 - Reserved
2 PAD40STRNG 0x0 RW
Pad 40 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD40INPEN 0x0 RW
Pad 40 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD40PULL 0x0 RW
Pad 40 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 647: PADREGL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD47FNC-
SEL
PAD47STRNG
PAD47INPEN
PAD47PULL
RSVD
PAD46FNC-
SEL
PAD46STRNG
PAD46INPEN
PAD46PULL
RSVD
PAD45FNC-
SEL
PAD45STRNG
PAD45INPEN
PAD45PULL
RSVD
PAD44FNC-
SEL
PAD44STRNG
PAD44INPEN
PAD44PULL
Table 646: PADREGK Register Bits
Bit Name Reset RW Description