User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 443 of 909 2019 Ambiq Micro, Inc.
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21:19 PAD42FNCSEL 0x3 RW
Pad 42 function select
UART1TX = 0x0 - Configure as the UART1 TX output signal
NCE42 = 0x1 - IOM/MSPI nCE group 42
CT16 = 0x2 - CTIMER connection 16
GPIO42 = 0x3 - Configure as GPIO42
M3SCL = 0x4 - Configure as the IOMSTR3 I2C SCL clock I/O signal
M3SCK = 0x5 - Configure as the IOMSTR3 SPI SCK output
RSVD6 = 0x6 - Reserved
RSVD7 = 0x7 - Reserved
18 PAD42STRNG 0x0 RW
Pad 42 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
17 PAD42INPEN 0x0 RW
Pad 42 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
16 PAD42PULL 0x0 RW
Pad 42 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
15 PAD41PWRDN 0x0 RW
Pad 41 power switch enable
DIS = 0x0 - Power switch disabled
EN = 0x1 - Power switch enabled (Switch pad to VSS)
14 RSVD 0x0 RO
RESERVED
13:11 PAD41FNCSEL 0x3 RW
Pad 41 function select
NCE41 = 0x0 - IOM/MSPI nCE group 41
RSVD = 0x1 - Reserved
SWO = 0x2 - Configure as the serial wire debug SWO signal
GPIO41 = 0x3 - Configure as GPIO41
I2SWCLK = 0x4 - I2S word clock input
UA1RTS = 0x5 - Configure as the UART1 RTS output signal
UART0TX = 0x6 - Configure as the UART0 TX output signal
UA0RTS = 0x7 - Configure as the UART0 RTS output signal
10 PAD41STRNG 0x0 RW
Pad 41 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
9 PAD41INPEN 0x0 RW
Pad 41 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
8 PAD41PULL 0x0 RW
Pad 41 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 646: PADREGK Register Bits
Bit Name Reset RW Description