User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 441 of 909 2019 Ambiq Micro, Inc.
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11.7.2.11PADREGK Register
Pad Configuration Register K (Pads 40-43)
OFFSET: 0x00000028
INSTANCE 0 ADDRESS: 0x40010028
This register controls the pad configuration controls for PAD43 through PAD40. Writes to this register must
be unlocked by the PADKEY register.
10 PAD37STRNG 0x0 RW
Pad 37 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
9 PAD37INPEN 0x0 RW
Pad 37 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
8 PAD37PULL 0x0 RW
Pad 37 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
7 RSVD 0x0 RO
RESERVED
6 PAD36PWRUP 0x0 RW
Pad 36 VDD power switch enable
DIS = 0x0 - Power switch disabled
EN = 0x1 - Power switch enabled (switched to VDD)
5:3 PAD36FNCSEL 0x3 RW
Pad 36 function select
TRIG1 = 0x0 - Configure as the ADC Trigger 1 signal
NCE36 = 0x1 - IOM/MSPI nCE group 36
UART1RX = 0x2 - Configure as the UART1 RX input signal
GPIO36 = 0x3 - Configure as GPIO36
32kHzXT = 0x4 - Configure as the 32kHz output clock from the crystal
UA1CTS = 0x5 - Configure as the UART1 CTS input signal
UA0CTS = 0x6 - Configure as the UART0 CTS input signal
PDMDATA = 0x7 - PDM serial data input
2 PAD36STRNG 0x0 RW
Pad 36 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD36INPEN 0x0 RW
Pad 36 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD36PULL 0x0 RW
Pad 36 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 644: PADREGJ Register Bits
Bit Name Reset RW Description